Channel coding: Theory, algorithms, and applications Academic Press Library in Mobile and Wireless Communications, 2014. ,
Low-density parity-check codes, IEEE Transactions on Information Theory, vol.8, issue.1, 1963. ,
DOI : 10.1109/TIT.1962.1057683
Performance and Complexity of 32 k-bit Binary LDPC Codes for Magnetic Recording Channels, IEEE Transactions on Magnetics, vol.46, issue.6, pp.2244-2247, 2010. ,
DOI : 10.1109/TMAG.2010.2043067
A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1450-1453, 2015. ,
DOI : 10.1109/ISCAS.2015.7168917
URL : https://hal.archives-ouvertes.fr/hal-00010871
On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, issue.2, pp.429-439, 2011. ,
DOI : 10.1109/TCSI.2010.2071990
Ldpc codes for the enhanced mobile broadband (embb) data channel in the 3gpp 5g new radio, pp.1-1 ,
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems, IEEE Communications Letters, vol.21, issue.5, pp.1-1, 2017. ,
DOI : 10.1109/LCOMM.2017.2656119
Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement, Proceedings of the 54th Annual Design Automation Conference 2017 on , DAC '17, pp.1-6, 2017. ,
DOI : 10.1007/978-3-319-27140-8_7
Fault-Tolerant Probabilistic Gradient-Descent Bit Flipping Decoder, IEEE Communications Letters, vol.18, issue.9, pp.1487-1490, 2014. ,
DOI : 10.1109/LCOMM.2014.2344031
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.64, issue.4, pp.906-917, 2017. ,
DOI : 10.1109/TCSI.2016.2633581
URL : https://hal.archives-ouvertes.fr/hal-01700290
A class of group-structured ldpc codes, Proc. 5th Int. Symp, 2001. ,
Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding, 2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), pp.300-304, 2016. ,
DOI : 10.1109/ISTC.2016.7593125
URL : https://hal.archives-ouvertes.fr/hal-01390467
Approaching maximum likelihood performance of ldpc codes by stochastic resonance in noisy iterative decoders, Information Theory and Applications Workshop, 2016. ,
Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers, IEEE Transactions on Computers, vol.63, issue.8, pp.1868-1881, 2014. ,
DOI : 10.1109/TC.2014.2315634
Efficient realization of probabilistic gradient descent bit flipping decoders, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1494-1497, 2015. ,
DOI : 10.1109/ISCAS.2015.7168928
URL : https://hal.archives-ouvertes.fr/hal-01700300
Noisy Gradient Descent Bit Flip Decoding of Low Density Parity Check Codes: Algorithm and Implementation. Doctoral dissertation, 2016. ,
Low Power Decoding of LDPC Codes, ISRN Sensor Networks, 2013. ,
DOI : 10.1109/JSSC.2005.864133
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units, 2016 Euromicro Conference on Digital System Design (DSD), pp.230-237, 2016. ,
DOI : 10.1109/DSD.2016.33
URL : https://hal.archives-ouvertes.fr/cea-01566283
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, p.114, 2017. ,
DOI : 10.1109/TVLSI.2017.2776561
URL : https://hal.archives-ouvertes.fr/hal-01700293
An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes, IEEE Communications Letters, p.1316, 2018. ,
DOI : 10.1109/LCOMM.2017.2718523
Approaching maximum likelihood performance of LDPC codes by stochastic resonance in noisy iterative decoders, 2016 Information Theory and Applications Workshop (ITA), pp.1-9, 2016. ,
DOI : 10.1109/ITA.2016.7888185
Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations, IEEE Transactions on Communications, pp.1-1, 2017. ,
DOI : 10.1109/TCOMM.2017.2778247
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes, IEEE Transactions on Circuits and Systems I: Regular Papers, pp.1-1, 2018. ,
DOI : 10.1109/TCSI.2017.2777802
URL : https://hal.archives-ouvertes.fr/hal-01695616
Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes, IEEE Transactions on Communications, pp.3385-3400, 2014. ,
DOI : 10.1109/TCOMM.2014.2356458
URL : https://hal.archives-ouvertes.fr/hal-01080871
VLSI Implementation of a High- Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes, IEEE Transactions on Circuits and Systems I: Regular Papers, pp.1083-1094, 2010. ,