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Article Dans Une Revue IEEE Transactions on Circuits and Systems I: Regular Papers Année : 2019

Hybrid Check Node Architectures for NB-LDPC Decoders

Résumé

This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC de-coders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.

Domaines

Electronique
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Dates et versions

hal-01874967 , version 1 (15-09-2018)

Identifiants

Citer

Cédric Marchand, Emmanuel Boutillon, Hassan Harb, Laura Conde-Canencia, Ali Al Ghouwayel. Hybrid Check Node Architectures for NB-LDPC Decoders. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66 (2), pp.869-880. ⟨10.1109/TCSI.2018.2866882⟩. ⟨hal-01874967⟩
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